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Precision Micropower, OVP, RRIO Operational Amplifier ADA4091-2/ADA4091-4
FEATURES
Single-supply operation: 2.7 V to 36 V Wide input voltage range Rail-to-rail output swing Low supply current: 200 A/amplifier Wide bandwidth: 1.2 MHz Slew rate: 0.46 V/s Low offset voltage: 250 V maximum No phase reversal Overvoltage protection (OVP) 25 V above/below supply rails at 5 V 12 V above/below supply rails at 15 V
PIN CONFIGURATIONS
OUTA 1 -INA 2 +INA 3 -V 4
8
+V OUTB
07671-001
ADA4091-2
TOP VIEW (Not to Scale)
7 6 5
-INB +INB
Figure 1. 8-Lead, Narrow-Body SOIC (R-8)
OUTA 1 -INA 2 +INA 3 -V 4 8 +V
ADA4091-2
TOP VIEW (Not to Scale)
7 OUTB 6 -INB 5 +INB
NOTES 1. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V-.
APPLICATIONS
Industrial process control Battery-powered instrumentation Power supply control and protection Telecommunications Remote sensors Low voltage strain gage amplifiers DAC output amplifiers
Figure 2. 8-Lead LFCSP (CP-8-9)
OUTA 1 -INA +INA
2 3 14 13
OUTD -IND +IND -V +INC -INC OUTC
07671-101
ADA4091-4
TOP VIEW (Not to Scale)
12 11 10 9 8
+V 4 +INB 5 -INB OUTB
6 7
14 OUTD
15 OUTA
GENERAL DESCRIPTION
The ADA4091-2 dual and ADA4091-4 quad are micropower, single-supply, 1.2 MHz bandwidth amplifiers featuring rail-torail inputs and outputs. They are guaranteed to operate from a +2.7 V to +30 V single supply as well as from 1.35 V to 15 V dual supplies. The ADA4091 family features a unique input stage that allows the input voltage to exceed either supply safely without any phase reversal or latch-up; this is called overvoltage protection, or OVP. Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezoelectric, and resistive transducers. The ability to swing rail-to-rail at both the input and output enables designers, for example, to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios (SNR). The ADA4091 family is specified over the extended industrial temperature range of -40C to +125C. The ADA4091 family is part of the growing selection of 36 V, low power op amps from Analog Devices, Inc., (see Table 1).
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 3. 14-Lead TSSOP (RU-14)
16 NC 13 NC
-INA 1 +INA 2 V+ 3 +INB 4
OUTC 7 OUTB 6 -INC 8 -INB 5
12 -IND
ADA4091-4
TOP VIEW
11 +IND 10 V- 9 +INC
NOTES 1. NC = NO CONNECT. 2. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V-.
Figure 4. 16-Lead LFCSP (CP-16-17)
The ADA4091-2 is available in 8-lead, plastic SOIC and 8-lead LFCSP packages. The ADA4091-4 is available in 14-lead TSSOP and 16-lead LFCSP surface-mount packages. Table 1. Low Power, 36 V Operational Amplifiers
Family Single Dual Quad Rail-to-Rail I/O ADA4091-2 ADA4091-4 PJFET AD8682 AD8684 Low Noise OP1177 OP2177 OP4177
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c)2008-2010 Analog Devices, Inc. All rights reserved.
07671-103
07571-102
ADA4091-2/ADA4091-4 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Pin Configurations ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Specifications ............................................................... 3 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution...................................................................................6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 14 Input Stage ................................................................................... 14 Output Stage................................................................................ 14 Input Overvoltage Protection ................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 18
REVISION HISTORY
5/10--Rev. D. to Rev. E Changes to Data Sheet Title ............................................................ 1 Changes to Table 2, Input Characteristics, Offset Voltage .......... 3 Changes to Table 3, Input Characteristics, Offset Voltage .......... 4 Changes to Table 4, Input Characteristics, Offset Voltage .......... 5 4/10--Rev. C to Rev. D Changes to Table 2, Added LFCSP to Input Characteristics ...... 3 Changes to Table 3, Added LFCSP to Input Characteristics ...... 4 Changes to Table 4, Added LFCSP to Input Characteristics ...... 5 10/09--Rev. B to Rev. C Added 8-Lead LFCSP and 16-Lead LFCSP ..................... Universal Change to Features Section ............................................................. 1 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 18 7/09--Rev. A to Rev. B Added New Part ADA4091-4 ........................................... Universal Changes to Features Section, General Description Section, and Figure 4 .............................................................................................. 1 Added Figure 2, Renumbered Sequentially .................................. 1 Changes to Table 1 ............................................................................ 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 4 Changes to Table 4 ............................................................................ 5 Changes to Table 5 ............................................................................ 6 Changes to Table 6 ............................................................................ 6 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 7/09--Rev. 0 to Rev. A Changes to Data Sheet Title .............................................................1 Changes to Features ..........................................................................1 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................4 Changes to Table 4.............................................................................5 Added Input Current Parameter, Table 5 .......................................6 Added New Figure 12 and Figure 13, Renumbered Sequentially ........................................................................................8 Added New Figure 24 and Figure 25 ........................................... 10 Added New Figure 36 and Figure 37 ........................................... 12 Added New Figure 43 .................................................................... 13 Changes to Input Overvoltage Protection Section..................... 15 Changes to Ordering Guide .......................................................... 16 10/08--Revision 0: Initial Version
Rev. E | Page 2 of 20
ADA4091-2/ADA4091-4 SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VSY = 1.5 V, VCM = 0.0 V, TA = 25C, unless otherwise noted. Table 2.
Parameter INPUT CHARACTERISTICS Offset Voltage Symbol VOS ADA4091-4 LFCSP package -40C TA +125C Offset Voltage Drift Input Bias Current VOS/T IB -40C TA +85C -40C TA +125C Input Offset Current IOS -40C TA +85C -40C TA +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain CMRR AVO VCM = -1.35 V to +1.35 V -40C TA +125C RL = 100 k, VO = -1.2 V to +1.2 V -40C TA +125C RL = 10 k, VO = -1.2 V to +1.2 V -40C TA +125C RL = 100 k to GND -40C TA +125C RL = 10 k to GND -40C to +125C RL = 100 k to GND -40C TA +125C RL = 10 k to GND -40C TA +125C Source/sink f = 1 MHz, AV = 1 VSY = 2.7 V to 36 V -40C TA +125C IO = 0 mA -40C TA +125C RL = 100 k, CL = 30 pF To 0.01% Test Conditions/Comments Min -250 -400 -600 -55 -55 -275 -3 -5 -75 -1.5 84 78 106 101 92 85 1.490 1.490 1.475 1.455 Typ -40 -40 2.5 -44 +55 +275 +3 +5 +75 +1.5 Max +250 +400 +600 Unit V V V V/C nA nA nA nA nA nA V dB dB dB dB dB dB V V V V V V V V mA dB dB A A V/s s MHz Degrees V p-p nV/Hz
0.5
100 113 94
OUTPUT CHARACTERISTICS Output Voltage High
VOH
1.495 1.485 -1.499 -1.495 31 102 -1.495 -1.495 -1.490 -1.490
Output Voltage Low
VOL
Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density
ISC ZOUT PSRR ISY
108 100
126 165 200 300
SR tS GBP M en p-p en
0.46 22 1.22 69 0.8 24
0.1 Hz to 10 Hz f = 1 kHz
Rev. E | Page 3 of 20
ADA4091-2/ADA4091-4
VSY = 5.0 V, VCM = 0.0 V, TA = 25C, unless otherwise noted. Table 3.
Parameter INPUT CHARACTERISTICS Offset Voltage Symbol VOS ADA4091-4 LFCSP package -40C TA +125C Offset Voltage Drift Input Bias Current VOS/T IB -40C TA +85C -40C TA +125C Input Offset Current IOS -40C TA +85C -40C TA +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain CMRR AVO VCM = -4.85 V to +4.85 V -40C TA +125C RL = 100 k, VO = 4.7 V -40C TA +125C RL = 10 k, VO = 4.7 V -40C TA +125C RL = 100 k to GND -40C TA +125C RL = 10 k to GND -40C TA +125C RL = 100 k to GND -40C TA +125C RL = 10 k to GND -40C TA +125C Source/sink f = 1 MHz, AV = 1 VSY = 2.7 V to 36 V -40C TA +125C IO = 0 mA -40C TA +125C RL = 100 k, CL = 30 pF To 0.01% Test Conditions/Comments Min -250 -400 -600 -60 -80 -350 -3 -7 -100 -5 95 88 113 106 98 90 4.980 4.980 4.950 4.900 Typ -45 -40 2.5 -50 +80 +350 +3 +7 +100 +5 Max +250 +400 +600 Unit V V V V/C nA nA nA nA nA nA V dB dB dB dB dB dB V V V V V V V V mA dB dB A A V/s s MHz Degrees V p-p nV/Hz
0.5
113 117 100
OUTPUT CHARACTERISTICS Output Voltage High
VOH
4.990 4.960 -4.998 -4.990 20 77 -4.990 -4.980 -4.980 -4.975
Output Voltage Low
VOL
Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density
ISC ZOUT PSRR ISY
108 100
126 180 225 300
SR tS GBP M en p-p en
0.46 22 1.22 70 0.8 24
0.1 Hz to 10 Hz f = 1 kHz
Rev. E | Page 4 of 20
ADA4091-2/ADA4091-4
VSY = 15.0 V, VCM = 0.0 V, VO = 0.0 V, TA = 25C, unless otherwise noted. Table 4.
Parameter INPUT CHARACTERISTICS Offset Voltage Symbol VOS ADA4091-4 LFCSP package -40C TA +125C Offset Voltage Drift Input Bias Current VOS/T IB -40C TA +85C -40C TA +125C Input Offset Current IOS -40C TA +85C -40C TA +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain CMRR AVO VCM = -14.85 V to +14.85 V -40C TA +125C RL = 100 k, VO = 14.7 V -40C TA +125C RL = 10 k, VO = 14.7 V -40C TA +125C RL = 100 k to GND -40C TA +125C RL = 10 k to GND -40C TA +125C RL = 100 k to GND -40C TA +125C RL = 10 k to GND -40C TA +125C Source/sink f = 1 MHz, AV = 1 VSY = 2.7 V to 36 V -40C TA +125C IO = 0 mA -40C TA +125C RL = 100 k, CL = 30 pF To 0.01% Test Conditions/Comments Min -250 -400 -600 -60 -80 -510 -3 -10 -140 -15 104 95 116 108 102 93 14.975 14.950 14.900 14.800 Typ -35 -40 3.0 -50 +80 +510 +3 +10 +140 +15 Max +250 +400 +600 Unit V V V V/C nA nA nA nA nA nA V dB dB dB dB dB dB V V V V V V V V mA dB dB A A V/s s MHz Degrees dB V p-p nV/Hz
0.5
121 119 104
OUTPUT CHARACTERISTICS Output Voltage High
VOH
14.980 14.920 -14.996 -14.975 20 71 -14.990 -14.985 -14.950 -14.940
Output Voltage Low
VOL
Short-Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density
ISC ZOUT PSRR ISY
108 100
126 200 250 350
SR tS GBP M CS en p-p en
f = 1 kHz 0.1 Hz to 10 Hz f = 1 kHz
0.46 22 1.27 72 100 0.8 25
Rev. E | Page 5 of 20
ADA4091-2/ADA4091-4 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage Input Voltage Differential Input Voltage Input Current Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec)
1
1
THERMAL RESISTANCE
Rating 36 V Refer to the Input Overvoltage Protection section VSY 5 mA Indefinite -65C to +150C -40C to +125C -65C to +150C 300C
JA is specified for the device soldered on a 4-layer JEDEC standard PCB with zero airflow. The exposed pad is soldered to the application board. Table 6. Thermal Resistance
Package Type 8-Lead SOIC (R-8) 14-Lead TSSOP (RU-14) 8-Lead LFCSP (CP-8-9) 16-Lead LFCSP (CP-16-17) JA 155 112 75 55 JC 45 35 12 14 Unit C/W C/W C/W C/W
ESD CAUTION
Input current should be limited to 5 mA.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. E | Page 6 of 20
ADA4091-2/ADA4091-4 TYPICAL PERFORMANCE CHARACTERISTICS
200 180 160 ADA4091-2 TA = 25C VSY = 1.5V
1000 10,000
NUMBER OF AMPLIFIERS
120 100 80 60 40 20
07671-034
VOUT TO RAIL (mV)
140
100 VDD - VOH 10
VOL - VSS 1 ADA4091-2 VSY = 1.5V
-250 -200 -150 -100 -50
0 VOS (V)
50
100
150
200
250
0.01
0.1
1
10
100
LOAD CURRENT (mA)
Figure 5. Input Offset Voltage Distribution
300 ADA4091-2 -40C TA +125C VSY = 1.5V
100
Figure 8. Dropout Voltage vs. Load Current
100 PHASE 80 80
250
NUMBER OF AMPLIFIERS
150
GAIN 40 40
100
20
20
50
0
ADA4091-2 VSY = 1.5V RL = 1M CL = 35pF 10k 100k FREQUENCY (Hz) 1M
0
07671-035
-1
0
1
2
3
4
5
6
7
8
TCVOS (V/C)
Figure 6. TCVOS Distribution
350 300 250 ADA4091-2 VSY = 1.5V
50
Figure 9. Open-Loop Gain and Phase vs. Frequency
AV = 100
40
CLOSED-LOOP GAIN (dB)
+125C 200 150
30 AV = 10 20 10 AV = 1 0 ADA4091-2 -10 V = 1.5V SY RL = 1M CL = 35pF -20 10 100
IB (nA)
100 50 +85C 0 -50 -100 -40C -150 -1.5 -1.0 -0.5 +25C
07671-033
0 VCM (V)
0.5
1.0
1.5
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 7. Input Bias Current vs. Common-Mode Voltage
Figure 10. Closed-Loop Gain vs. Frequency
Rev. E | Page 7 of 20
07671-010
07671-007
0
-20 1k
-20 10M
PHASE (Degrees)
200
OPEN-LOOP GAIN (dB)
60
60
07671-017
0
0.1 0.001
ADA4091-2/ADA4091-4
1k
3.0
2.5
100 AV = 100
VOUT SWING (V)
AV = 1 ADA4091-2 TA = 25C VSY = 1.5V
07671-013
2.0
ZOUT ()
10 AV = 10
1.5
1.0
1
0.5
ADA4091-2 VSY = 1.5V VIN = 2.8V p-p RL = 100k 1k 10k FREQUENCY (Hz) 100k 1M
07671-036
07671-045
07671-051
0.1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
0 100
Figure 11. Output Impedance vs. Frequency
2.0 1.5 1.0
1.6 1.4 1.2
Figure 14. Output Swing vs. Frequency
OUTPUT VOLTAGE (V)
1.0 0.8 0.6 0.4 0.2 0 ADA4091-2 TA = 25C VSY = 1.5V 0 10 20 30 40 50 TIME (s) 60 70 80 90
0.5
VOUT (V)
0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25 TIME (s) 30 35 40 45 50 ADA4091-2 VSY = 1.5V TA = 25C RL = 100k CL = 100pF AV = +1
07671-025
-0.2
Figure 12. Large Signal Transient Response
0.06 0.04
Figure 15. Positive Overload Recovery
0 -0.2 -0.4
OUTPUT VOLTAGE (V)
0.02
-0.6 -0.8 -1.0 -1.2 -1.4 -1.6 0 10 20 30 40 50 TIME (s) 60 70 80 90 ADA4091-2 TA = 25C VSY = 1.5V
VOUT (V)
0 ADA4091-2 VSY = 1.5V TA = 25C RL = 100k CL = 100pF AV = +1
-0.02
-0.04
-0.06
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (s)
07671-028
-0.08
Figure 13. Small Signal Transient Response
Figure 16. Negative Overload Recovery
Rev. E | Page 8 of 20
ADA4091-2/ADA4091-4
225 200 175
0.02 0.06
ADA4091-2 TA = 25C VSY = 5V
0.04
NUMBER OF AMPLIFIERS
150 125 100 75
-0.04
VOUT (V)
0 -0.02
ADA4091-2 VSY = 5V TA = 25C RL = 100k CL = 100pF AV = +1
50 25
07671-037
-0.06 -0.08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (s)
-250 -200 -150 -100 -50
0 VOS (V)
50
100
150
200
250
Figure 17. Input Offset Voltage Distribution
400 350 ADA4091-2 -40C TA +125C VSY = 5V
500 400
Figure 20. Small Signal Transient Response
ADA4091-2 VSY = 5V
NUMBER OF AMPLIFIERS
300 250 200 150 100 50
07671-038
300 200 100 +125C +85C 0 +25C
IB (nA)
-100 -40C -200 -5
-1
0
1
2
3
4
5
6
7
8
-4
-3
-2
-1
0 VCM (V)
1
2
3
4
5
TCVOS (V/C)
Figure 18. TCVOS Distribution
6 100
Figure 21. Input Bias Current vs. Common-Mode Voltage
100 PHASE
4
80
80
OPEN-LOOP GAIN (dB)
0
-2
ADA4091-2 VSY = 5V TA = 25C RL = 100k CL = 100pF AV = +1
40
GAIN
40
20
20
-4
07671-026
0
5
10
15
20
25 TIME (s)
30
35
40
45
50
100k FREQUENCY (Hz)
1M
Figure 19. Large Signal Transient Response
Figure 22. Open-Loop Gain and Phase vs. Frequency
Rev. E | Page 9 of 20
07671-005
-6
0 ADA4091-2 VSY = 5V RL = 1M CL = 35pF -20 1k 10k
0
-20 10M
PHASE (Degrees)
2
60
60
VOUT (V)
07671-032
0
07671-029
0
ADA4091-2/ADA4091-4
1k
50
AV = 100
40
CLOSED-LOOP GAIN (dB)
100
30 AV = 10 20
ZOUT ()
AV = 100 10
10 AV = 1 0 ADA4091-2 -10 VSY = 5V RL = 1M CL = 35pF -20 10 100
AV = 10 1 AV = 1 0.1 10 100 1k 10k 100k FREQUENCY (Hz) ADA4091-2 TA = 25C VSY = 5V
07671-012
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 23. Output Impedance vs. Frequency
10 9
Figure 26. Closed-Loop Gain vs. Frequency
6
5
8 7
OUTPUT VOLTAGE (V)
VOUT SWING (V)
4
6 5 4 3 2 ADA4091-2 VSY = 5V 1 VIN = 9.8V p-p RL = 100k 0 100 1k
3
2
10k FREQUENCY (Hz)
100k
1M
07671-015
30
40 50 TIME (s)
60
70
80
90
Figure 24. Output Voltage Swing vs. Frequency
10,000
Figure 27. Positive Overload Recovery
1 0
1000
100
VDD - VOH
OUTPUT VOLTAGE (V)
-1 -2
VOUT TO RAIL (mV)
10
VOL - VSS
-3 -4 -5 ADA4091-2 TA = 25C VSY = 5V 0 10 20 30 40 50 TIME (s) 60 70 80
07671-047
1 ADA4091-2 VSY = 5V 0.01 0.1 1 10 100 LOAD CURRENT (mA)
07671-018
0.1 0.001
-6
Figure 25. Dropout Voltage vs. Load Current
Figure 28. Negative Overload Recovery
Rev. E | Page 10 of 20
07671-046
1 ADA4091-2 TA = 25C VSY = 5V 0 0 10 20
07671-009
ADA4091-2/ADA4091-4
250 ADA4091-2 TA = 25C VSY = 15V 200
100 PHASE 80 80 100
NUMBER OF AMPLIFIERS
OPEN-LOOP GAIN (dB)
150
40
GAIN
40
100
20
20
50
07671-041
-250 -200 -150 -100 -50
0 VOS (V)
50
100
150
200
250
100k FREQUENCY (Hz)
1M
Figure 29. Input Offset Voltage Distribution
350 300 ADA4091-2 -40C TA +125C VSY = 15V
20 15 10 5
Figure 32. Open-Loop Gain and Phase vs. Frequency
NUMBER OF AMPLIFIERS
250 200
VOUT (V)
0 -5
150 100
-10 -15
07671-042
ADA4091-2 VSY = 15V TA = 25C RL = 100k CL = 100pF AV = +1
50 0 -1 0 1 2 3 4 5 6 7 8 TCVOS (V/C)
0
25
50
75
100
125
150
175
200
TIME (s)
Figure 30. TCVOS Distribution
700 600 500 400 +125C
0.02 0.06 0.04
Figure 33. Large Signal Transient Response
ADA4091-2 VSY = 15V
200 100 0 -100 -40C -200
07671-031
VOUT (V)
300
IB (nA)
0 -0.02 -0.04
+85C
+25C
ADA4091-2 VSY = 15V TA = 25C RL = 100k CL = 100pF AV = +1
-0.06 -0.08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (s)
-10
-5
0 VCM (V)
5
10
15
Figure 31. Input Bias Current vs. Common-Mode Voltage
Figure 34. Small Signal Transient Response
Rev. E | Page 11 of 20
07671-030
-300 -15
07671-027
-20 -25
07671-006
0
0 ADA4091-2 VSY = 15V RL = 1M CL = 35pF -20 1k 10k
0
-20 10M
PHASE (Degrees)
60
60
ADA4091-2/ADA4091-4
35 30
50 40
AV = 100
25
CLOSED-LOOP GAIN (dB)
30 20 10 AV = 1 0 -10 ADA4091-2 -20 VSY = 15V RL = 1M CL = 35pF -30 10 100 AV = 10
VOUT SWING (V)
20
15
10 ADA4091-2 5 VSY = 15V VIN = 29.8V p-p RL = 100k 0 100 1k
07671-016
10k FREQUENCY (Hz)
100k
1M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Output Voltage Swing vs. Frequency
10,000
16 14
Figure 38. Closed-Loop Gain vs. Frequency
1000
12
OUTPUT VOLTAGE (V)
VOUT TO RAIL (mV)
100
VDD - VOH
10 8 6 4 2
10
VOL - VSS
1 ADA4091-2 VSY = 15V
07671-019
0 -2 0
0.01
0.1
1
10
100
10
20
30
LOAD CURRENT (mA)
40 50 TIME (s)
60
70
80
90
Figure 36. Dropout Voltage vs. Load Current
1k
Figure 39. Positive Overload Recovery
2 0
100
-2
OUTPUT VOLTAGE (V)
-4 -6 -8 -10 -12
ZOUT ()
10
AV = 100
1
AV = 10
AV = 1
07671-011
100
1k
10k
100k
1M
10M
0
10
20
30
FREQUENCY (Hz)
40 50 TIME (s)
60
70
80
Figure 37. Output Impedance vs. Frequency
Figure 40. Negative Overload Recovery
Rev. E | Page 12 of 20
07671-049
0.1 10
ADA4091-2 TA = 25C VSY = 15V
-14 -16
ADA4091-2 TA = 25C VSY = 15V
07671-048
0.1 0.001
ADA4091-2 TA = 25C VSY = 15V
07671-008
ADA4091-2/ADA4091-4
0.5 0.4 0.3 0.2
80 100 ADA4091-2 VSY = 1.5V, 5V, 15V
60
NOISE (V p-p)
PSRR (dB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) ADA4091-2 VSY = 15V
07671-043
PSRR- 40
PSRR+
20
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 41.Peak-to-Peak Voltage Noise
-60 ADA4091-2 VSY = 15V -70
Figure 44. PSRR vs. Frequency
500
ADA4091-2 450 TA = 25C
CHANNEL SEPARATION (dB)
400
-80
350 300
ISY (A)
-90
250 200 150 100
-100
-110
-120
50
07671-044
10
100
1k FREQUENCY (Hz)
10k
100k
0
5
10
15
20 VSY (V)
25
30
35
Figure 42. Channel Separation vs. Frequency
110 100 90 80 70 VSY = 5V, 15V
Figure 45. Supply Current vs. Supply Voltage
1k
ADA4091-2
CMRR (dB)
VSY = 1.5V
60 50 40 30 20 10
07671-002
VOLTAGE NOISE (nV/ Hz)
100
ADA4091-2 TA = 25C VSY = 5V
1k 10k 100k 1M 10M
0.1
FREQUENCY (Hz)
1 10 FREQUENCY (Hz)
100
1k
Figure 43. CMRR vs. Frequency
Figure 46. Voltage Noise Density
Rev. E | Page 13 of 20
07671-050
0 100
10 0.01
07671-004
-130
0
07671-003
-20 100
ADA4091-2/ADA4091-4 THEORY OF OPERATION
The ADA4091 family is a single-supply, micropower amplifier featuring rail-to-rail inputs and outputs. To achieve wide input and output ranges, these amplifiers employ unique input and output stages. Q1 and Q2 are high enough to turn on Q3, which diverts the tail current away from the PNP input stage, turning it off. The tail current of the PNP pair is diverted to the Q4/Q7 current mirror to activate the NPN input stage. A common practice in bipolar amplifiers to protect the input transistors from large differential voltages is to include series resistors and differential diodes. See Figure 48 for the full input protection circuitry. These diodes turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current flows between the input pins, limited only by the two 5 k resistors. Evaluate each application carefully to make sure that the increase in current does not affect performance.
INPUT STAGE
In Figure 47, the input stage comprises two differential pairs, a PNP pair (PNP input stage) and an NPN pair (NPN input stage). These input stages do not work in parallel. Instead, only one stage is on for any given input common-mode signal level. The PNP stage (Transistor Q1 and Transistor Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. Alternatively, the NPN stage (Transistor Q5 and Transistor Q6) is needed for input voltages up to, and including, the positive rail. For the majority of the input common-mode range, the PNP stage is active, as shown in Figure 7, Figure 21, and Figure 31. Notice that the bias current switches direction at approximately 1.5 V below the positive rail. At voltages below this level, the bias current flows out of the ADA4091-x input, from the PNP input stage. Above this voltage, however, the bias current enters the device, due to the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises Transistor Q3, Transistor Q4, and Transistor Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of
OUTPUT STAGE
The output stage in the ADA4091-x device uses a PNP and an NPN transistor, as do most output stages. However, Q32 and Q33, the output transistors, connect with their collectors to the output pin to achieve the rail-to-rail output swing. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage has inherent gain arising from the transistor output impedance, as well as any external load impedance; consequently, the open-loop gain of the op amp is dependent on the load resistance and decreases when the output voltage is close to either rail.
-IN
Q32
Q3
+IN
Q1 Q2
Q5 Q6 Q8 Q10
Q12 Q14
Q16
Q17 OUT
Q9
Q11
Q13
Q15
Q18
Q19
Q33
07671-024
Q4
Q7
Figure 47. Simplified Schematic Without Input Protection (see Figure 48)
Rev. E | Page 14 of 20
ADA4091-2/ADA4091-4
INPUT OVERVOLTAGE PROTECTION
The ADA4091-x has two different ESD circuits for enhanced protection, as shown in Figure 48. For a worst-case design analysis, consider two cases. The ADA4091-x has a normal ESD structure from the internal op amp inputs to the supply rails. In addition, it has 42 V DIACs from the external inputs to the rails, as shown in Figure 47. Therefore, two conditions need to be considered to determine which case is the limiting factor.
+V
*
D3 R1 D7 R2 D8 D5 D6 D4
D1 D2
Condition 1. Consider, for example, that when operating on 15 V, the inputs can go +42 V above the negative supply rail. With the -V pin equal to -15 V, +42 V above this supply (the negative supply) is +27 V. Condition 2. There is a restriction on the input current of 5 mA through a 5 k resistor to the ESD structure to the positive rail. In Condition 1, +27 V through the 5 k resistor to +15 V gives a current of 2.4 mA. Thus, the DIAC is the limiting factor. If the ADA4091-x supply voltages are changed to 5 V, then -5 V + 42 V = +37 V. However, +5 V + (5 k x 5 mA) = 30 V. Thus, the normal resistor diode structure is the limitation when running on lower supply voltages.
*
-V
07671-023
Figure 48. Complete Input Protection Network
One circuit is a series resistor of 5 k to the internal inputs and diodes (D1 and D2 or D5 and D6) from the internal inputs to the supply rails. The other protection circuit is a circuit with two DIACs (D3 and D4 or D7 and D8) to the supply rails. A DIAC can be considered a bidirectional Zener diode with a transfer characteristic, as shown in Figure 49.
5 4 3
Additional resistance can be added externally in series with each input to protect against higher peak voltages; however, the additional thermal noise of the resistors must be considered. The flatband voltage noise of the ADA4091-x is approximately 24 nV/Hz, and a 5 k resistor has a noise of 9 nV/Hz. Adding an additional 5 k resistor increases the total noise by less than 15% root sum square (rss). Therefore, maintain resistor values below this value (5 k) when overall noise performance is critical. Note that this represents input protection under abnormal conditions only. The correct amplifier operation input voltage range (IVR) is specified in Table 2, Table 3, and Table 4.
CURRENT (mA)
2 1 0 -1 -2
07671-100
-3 -50
-40
-30
-20
-10
0
10
20
30
40
50
VOLTAGE (V)
Figure 49. DIAC Transfer Characteristic
Rev. E | Page 15 of 20
ADA4091-2/ADA4091-4 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8
5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2441) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
0.51 (0.0201) 0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
3.25 3.00 SQ 2.75
0.60 MAX 0.60 MAX
5 8
0.50 BSC
PIN 1 INDICATOR
2.95 2.75 SQ 2.55
EXPOSED PAD
1.60 1.50 1.40 PIN 1 INDICATOR
4
TOP VIEW
1
12 MAX 0.90 MAX 0.85 NOM SEATING PLANE
0.70 MAX 0.65 TYP
0.50 0.40 0.30 0.05 MAX 0.01 NOM
BOTTOM VIEW
2.23 2.13 2.03
0.30 0.23 0.18
0.20 REF
Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-9) Dimensions shown in millimeters
Rev. E | Page 16 of 20
051909-A
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
012407-A
ADA4091-2/ADA4091-4
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 0.65 BSC 1.05 1.00 0.80 0.15 0.05 COPLANARITY 0.10 1.20 MAX
0.20 0.09 8 0
0.30 0.19
SEATING PLANE
0.75 0.60 0.45
061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
PIN 1 INDICATOR
4.10 4.00 SQ 3.90 0.65 BSC
0.35 0.30 0.25
13 12 EXPOSED PAD 1 16
PIN 1 INDICATOR
4 9 8 5
2.70 2.60 SQ 2.50
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.45 0.40 0.35
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions are millimeters
Rev. E | Page 17 of 20
012909-B
ADA4091-2/ADA4091-4
ORDERING GUIDE
Model 1 ADA4091-2ARZ ADA4091-2ARZ-R7 ADA4091-2ARZ-RL ADA4091-2ACPZ-R2 ADA4091-2ACPZ-R7 ADA4091-2ACPZ-RL ADA4091-4ARUZ ADA4091-4ARUZ-RL ADA4091-4ACPZ-R2 ADA4091-4ACPZ-R7 ADA4091-4ACPZ-RL
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Frame Chip Scale Package (LFCSP_VD) 14-Lead Thin Shrink Small Outline Package (TSSOP) 14-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
Package Option R-8 R-8 R-8 CP-8-9 CP-8-9 CP-8-9 RU-14 RU-14 CP-16-17 CP-16-17 CP-16-17
Branding
A1Z A1Z A1Z
Z = RoHS Compliant Part.
Rev. E | Page 18 of 20
ADA4091-2/ADA4091-4 NOTES
Rev. E | Page 19 of 20
ADA4091-2/ADA4091-4 NOTES
(c)2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07671-0-5/10(E)
Rev. E | Page 20 of 20

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